Many ICs are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. Complementary metal-oxide semiconductors (“CMOS”) circuits and fabrication technology are commonly used in complex ICs. CMOS circuits use P-channel metal-oxide semiconductor (“PMOS”) and N-channel metal-oxide semiconductor (“NMOS”) devices to implement functions such as logic and input/output (“I/O”) blocks.
An I/O block is a circuit in an IC that receives or sends data from or to other ICs. Signals can be differential (i.e., a HI/LOW or LOW/HI signal is simultaneously provided on differential I/O pins) or single-ended (i.e., either a HI signal or a LOW signal is provided on a single pin). In some ICs, I/O blocks can operate on either differential signals or on single-ended signals. When the I/O block operates in differential mode, an on-die differential termination is provided to terminate the differential path with an appropriate impedance (load resistor). When the I/O block operates in single ended mode, the differential termination is turned off.
I/O pads are often user-accessible, which makes components in the I/O circuit susceptible to damage from electro-static discharge (“ESD”). ICs with I/O circuits typically must pass an ESD specification wherein a human body model (“HBM”), a machine model (“MM”), or a charged device model (“CDM”) is charged to a specified voltage (e.g., a few kV for an HBM, 100-200 V for a MM, or several hundred Volts for a CDM) and then discharged onto the I/O pad. The inrush of current occurring when a charged HBM or CDM is connected to a pad of the I/O block can destroy components, such as field-effect transistors (“FETs”), and damage or destroy the functionality of the I/O circuit. Several techniques have been developed to protect against ESD damage.
An ESD can be a negative voltage or a positive voltage, relative to circuit ground. In a CMOS I/O circuit, ESD protection to both the PMOS devices and the NMOS devices is used. One technique is to connect one ESD element (e.g., diode or silicon-controlled rectifier (“SCR”)) between a pad and ground, and another ESD element between the pad and a voltage supply, such as Vcco, to discharge current associated with a positive or negative ESD event (“zap”). Techniques using an SCR(s) often include a resistor in series between the SCR and data input, which develops bias voltage to trigger the SCR during an ESD event, but also degrades signal discrimination.
Another approach uses an SCR in parallel with a diode between ground and the input pin. A series resistor between the SCR and downstream circuit elements biases the SCR to discharge if a positive (voltage) ESD event occurs, and the diode discharges current in reverse breakdown if a negative ESD event occurs (or vice versa). However, the series resistor also degrades signal strength during normal operation.
Conventional ESD elements are relatively big in order to handle the discharge current without being damaged. Differential drivers are often low-voltage and relatively weak (small) devices requiring ESD protection in addition to the protection for the single-ended drivers in a differential/single selectable I/O. In ICs having a relatively high number of I/O pads, such as field-programmable gate arrays (“FPGAs”), providing ESD protection to all components for I/Os susceptible to ESD damage consumes considerable silicon area.
Another approach is to use silicide blocking techniques, which basically increases impedance for the drain current (e.g., similar to a ballast resistor) so that current from an ESD event is conducted from the drain of the FET into the well or substrate and further to ground or Vcco pins.
ESD protection with reduced silicon area for I/O circuit components is desirable.